1. Field of the Invention
The present invention relates to a display control circuit and a display control method for use with a display system in an information processing apparatus (OA apparatus) such as a personal digital assistant and a portable computer, which uses an LCD (liquid crystal display) device.
2. Description of the Related Art
An LCD device has a small size and low power consumption, and therefore is typically used in an information processing apparatus such as a personal digital assistant and a portable computer. Among others, an STN (super-twisted nematic) reflection-type LCD device is used widely since it is less expensive than a TFT (thin film transistor) LCD device and still is capable of providing a relatively large capacity display (several hundredsxc3x97several hundreds pixels).
The primary display mode of the STN LCD device is a black and white binary display mode (hereinafter, referred to simply as a xe2x80x9cbinary display modexe2x80x9d). However, using the same binary-display LCD device, a gray-scale display can also be performed by modifying the signal application to the device.
Japanese Laid-open Publication No. 2-120792 discloses a frame modulation method (also called a xe2x80x9cframe thinning methodxe2x80x9d) which is typically employed for performing a gray-scale display in an STN LCD device. In this method, the amount of display data per pixel input to an LCD driver is the same as that in the binary display mode (one bit per pixel). However, unlike the binary display mode, a display data signal on a certain display data signal line is controlled for each xe2x80x9cframexe2x80x9d (a period of time in which display data signals for one screen are sent to the LCD device), so as to realize a gray-scale display.
For example, in order to display white (or black) on a pixel for a certain period of time, a white (or black) signal is provided to the LCD driver via a corresponding display data signal line at a timing corresponding to the pixel position for a set of frames according to the period of time. In order to display a gray-scale level on the pixel for the period of time, either a white or black signal is provided to the LCD driver for each of the set of frames according to the period of time. The gray-scale level of the pixel for the period of time is defined by the frame number ratio between the white signal and the black signal which are sent to the LCD driver during the period of time.
In such a gray-scale display system employing the frame thinning method, specific timings of various control signals for driving the LCD driver can be the same as those in the binary display mode. However, in order to avoid display quality deterioration such as flicker, it is necessary to use a frame frequency which is different from that employed in the binary display mode.
The flicker in the STN LCD device is caused by interference between blinking of a fluorescent lamp (due to the supplied electric current alternating at the commercial power frequency) and changes in the brightness of the LCD. Since the frequency at which the brightness of the LCD changes is determined by the frame frequency, the appropriate selection of frame frequency is critical. Typically, the frame frequency is set to 70 Hz for the binary display mode. When the frame frequency is set to 70 Hz, flicker is substantially imperceivable either when the commercial power frequency is 50 Hz (as in eastern Japan) or when the commercial power frequency is 60 Hz (as in western Japan).
However, when the frame thinning method is employed with the frame frequency of 70 Hz, flicker becomes conspicuous, and the display quality considerably deteriorates. A higher frame frequency should be used for the gray-scale display based on the frame thinning method. While the appropriate frame frequency varies depending upon the characteristics of the particular LCD device, when the frame frequency is increased to about 140 Hz for such a gray-scale display, the gray-scale display can be performed with hardly any flicker.
When the system is intended to perform only one of the binary display and the gray-scale display (as is typical in a conventional display system), such a consideration of the frame frequency is not necessary for the LCD controller.
When a single display system is intended to be used for both the binary display and the gray-scale display, two different oscillators are conventionally provided for generating two different clock signals for the two different frame frequencies, or a single oscillator is provided for generating a single clock signal while performing both the gray-scale display and the binary display at the same frame frequency (e.g., 140 Hz).
As described above, the binary display and the gray-scale display have different optimal LCD frame frequencies (and thus different optimal operating clock frequencies for the LCD controller).
In addition, as described above, a system intended to perform both the binary display and the gray-scale display conventionally employs two different oscillators for obtaining two different oscillation frequencies so that the optimal frame frequency can be obtained both in the binary display and in the gray-scale display.
However, providing two different oscillators is disadvantageous in terms of circuit scale and cost.
The optimal frame frequency for the gray-scale display (e.g., 140 Hz) also may be used for the binary display, instead of providing two different frame frequencies. In such a case, although flicker does not occur in the binary display, the power consumption increases because of the high frame frequency of 140 Hz being used for the binary display, which requires only 70 Hz. The power consumption of the LCD device increases in proportion to the driving frame frequency. Moreover, an increase in the frame frequency leads to an increase in the LCD controller operating clock frequency and thus an increase in the power consumption of the LCD controller circuit.
According to one aspect of this invention, a display control circuit includes: a clock generator for generating a first clock signal having a single frequency; a frequency divider for dividing the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal; a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
In one embodiment of the invention, the frequency divider further comprises a blocking section for blocking the frequency divider from receiving the first clock signal when the selector selects the first clock signal.
In one embodiment of the invention, the display control circuit further includes a voltage adjustment section for adjusting a display device driving voltage based on the selection signal when the display circuit variably controls a timing of a control signal output to a display device.
According to another aspect of this invention, a display control circuit includes: a clock generator for generating a first clock signal having a single frequency; a frequency multiplier for multiplying the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal; a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
In one embodiment of the invention, the display control circuit further includes a voltage adjustment section for adjusting a display device driving voltage based on the selection signal when the display circuit variably controls a timing of a control signal output to a display device.
According to still another aspect of this invention, a display control method includes the steps of: generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; selecting one of a first clock signal and a second clock signal obtained by dividing the frequency of the first clock signal based on the selection signal; and performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
In one embodiment of the invention, the display control method further includes the step of generating one of a display setting voltage for the binary display mode and a display setting voltage for the gray-scale display mode based on the selection signal.
According to still another aspect of this invention, a display control method includes the steps of: generating a selection signal upon which one of a binary display and a gray-scale display is selected; selecting one of a first clock signal and a second clock signal obtained by multiplying the frequency of the first clock signal based on the selection signal; and performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
In one embodiment of the invention, the display control method further includes the step of generating one of a display setting voltage for the binary display mode and a display setting voltage for the gray-scale display mode based on the selection signal.
Thus, the invention described herein makes possible the advantages of (1) providing a display control circuit for performing both a binary display and a gray-scale display without increasing the power consumption when performing the binary display; and (2) providing a display control method for the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.